FIG. 1 illustrates a conventional voltage level shifting circuit 100 for translating an input signal IN having an input voltage level V1 to an output signal OUT having an output voltage level V2. The voltage level shifting circuit 100 includes p-channel MOS (PMOS) pull-up transistors 104 and 108 coupled to a voltage supply providing the voltage level V2. Coupled to the PMOS pull-up transistors 104, 108 are PMOS load transistors 120, 124 and n-channel MOS (NMOS) pull-down transistors 112, 116, all respectively. Gates of the PMOS load transistors 120, 124 and of the NMOS pull-down transistors 112, 116 are coupled to receive the IN signal having the V1 voltage level through series coupled inverters 150, 154. The OUT signal having the V2 voltage level is provided at an output node 134.
In operation, a falling edge of the IN signal causes the NMOS pull-down transistor 112 and the PMOS load transistor 124 to switch ON, and the NMOS pull-down transistor 116 and the PMOS load transistor 120 to switch OFF. In this state, the gate of the PMOS pull-up transistor 108 is coupled to ground, switching ON the PMOS pull-up transistor 108. With both the PMOS pull-up transistor 108 and the PMOS load transistor 124 switched ON, the output node is coupled to the V2 voltage supply. In response to a rising edge of the IN signal, the PMOS load transistor 120 and the NMOS pull-down transistor 116 are switched ON, and the PMOS load transistor 124 and the NMOS pull-down transistor 112 are switched OFF. As a result, the output node 134 is coupled to ground through the NMOS pull-down transistor 116. As the voltage of the output node 134 is pulled to ground, the PMOS pull-up transistor 104 eventually switches ON to couple the gate of the PMOS pull-up transistor 108 to the V2 voltage supply 106, thereby switching OFF the PMOS pull-up transistor 108 and decoupling the output node 134 from the V2 voltage supply 106. When the output node 134 is decoupled from the V2 voltage supply 106, the voltage of the output node 134 is finally pulled to ground.
The performance of the conventional voltage level shifting circuit 100 begins to suffer as the voltage difference between the input and output signals becomes greater. That is, the voltage difference between the input and output signals affects the speed at which the PMOS pull-up transistors 104, 108 and PMOS load transistors 120, 124 switch OFF, which in turn, specifically with respect to the PMOS pull-up transistor 108 and the PMOS load transistor 124, directly affects the speed at which the voltage at the output node 134 can be pulled to ground.
As previously described, a rising edge of the IN signal causes the NMOS pull-down transistor 116 to switch ON, thereby coupling the output node 134 to ground. However, at this time, the PMOS pull-up transistor 108 and the PMOS load transistor 124 are still ON because the threshold voltages for both transistors are still exceeded. With a large voltage difference between the V2 voltage level and the V1 voltage level, a large voltage swing must occur before the voltage at the gates of the PMOS pull-transistor 108 and the PMOS load transistor 124 relative to the voltage at the sources of the two transistors will decrease below the respective threshold voltages to switch the transistors OFF. Before the PMOS pull-up transistor 108 and the PMOS load transistor 124 are switched OFF, it is difficult for the NMOS pull-down transistor 116 to pull the output node LOW and because current is sunk through the NMOS pull-down transistor 116 to ground, power consumption is high. Finally, when the voltage of the output node 134 decreases enough so that the threshold voltage of the PMOS pull-up transistor 104 is exceeded, switching OFF the PMOS pull-up transistor 108 is accelerated due to the coupling of its gate to the V2 voltage supply. Although the PMOS load transistors 120 and 124 can be used to mitigate the problem by having device dimensions that can lower the voltage at the output node 134, as well as limit the current consumption, the current drive capability of the voltage level shifting circuit 100 is compromised as a result.